IDC Design Engineer

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Description

IT Infrastructure MNC seeking a IDC Design Engineer to join our Serdes Technology Group in the Programmable Platform Group and perform the following key activities:

Permanent/ Contract roles are available.  

Job Description : 

• Develop and implement plans to synthesize, implement Design-For-Test (DFT) and close timing on complex digital integrated circuits at the block, subsystem or device level (100K to 10M+ gates) which are coded in VHDL/Verilog.

• Work with various design groups across different disciplines (Logic, Circuits, DFT & Layout) to meet timing closure, area, power, and performance requirements.

• Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies.

• Analyze log and report files to ensure the tools are getting the required results and make adjustments to the scripts to get the required results within the scheduled milestones.

• Communicate regularly with the project teams world-wide to resolve issues and to ensure meeting targeted goals and schedule.

The successful candidate should be/possess the following:

• Bachelor/Masters Degree in Electrical/Computer Engineering

• Strong scripting skills in Perl, TCL and Shell, particularly in synthesis & timing algorithms, with good understanding of UNIX/LINUX.

• Able to work autonomously as well as in a team environment across multiple geographical sites, with a strong desire to succeed.

• Excellent debugging, problem solving and analytical skills.

• Excellent communication and interpersonal skills.

Basic : >5k, with bonuses. CPF contribution for Singaporeans inclusive.

Keen to apply for this role?

Please email a copy of your resume, photo, reasons for leaving, details of your current/ last drawn and expected salary to : socrates3142@gmail.com

Regret to notify that only shortlisted candidates will proceed for the interview and will be contacted by our recruiters for the arrangement for the interview. 

Thank you.